Techniques for manufacturing seminconductor devices such as integrated circuits continue to improve. Present photolithography equipment allows minimum line widths of 0.18 .mu.m in current generation devices. Sub-0.15 .mu.m line widths will be available for next-generation devices. These narrow line widths create fabrication and operational problems in all structures of an integrated circuit. Among these affected structures are polysilicon gates of field effect transistors and metalization used for electrical interconnect.
One solution proposed for application to sub-0.25 .mu.m complimentary metal-oxide-semiconductor (CMOS) integrated circuits is using silicide materials such as titanium silicide, cobalt silicide and nickel silicide. Conventionally, the metal is blanket deposited on the surface of a metal semi-conductor wafer during fabrication. However, this can result in short circuit failures between the gate and source/drain, known as bridging. Such failures occur, particularly in the case of titanium silicide, because most of the silicidation takes place in the metal area deposited on the silicon wafer. Silicon atoms are drawn in from the silicon gate source/drain regions. Titanium silicide has a further problem in the form of narrow line effects, such as disconnected grains, in the titanium silicide.
Accordingly, there is a need for a technique for manufacturing a field effect transistor and an integrated circuit which overcomes these and other problems.